The present invention relates to a semiconductor integrated circuit structure, such as a wafer, having a plurality of chips in the form of strips which are to be separated, after manufacture, along scribe lines.
In the manufacture of integrated circuits, such as LSI circuits, is known to utilize a hybrid alignment method based on general photolithographic principles.
Hybrid alignment methods employ two types of exposure systems: stepping projection, or stepper: and scanning projection, or scanner. In a stepping projection system, each pattern is produced by reduction imaging, with a reduction ratio of 5:1 or 10:1, utilizing exposure equipment including a stepper. This system is employed when high resolution and accurate alignment are necessary. The scanning projection system involves a projection aligner in which the imaging ratio is 1:1. An optical system is disposed between the mask and the semiconductor wafer to project an image of the mask pattern onto the wafer. Mask deterioration is avoided because the mask does not contact the wafer. This system is employed when the particular operation does not require high resolution or accurate alignment. The advantages of the hybrid alignment method include a low total cost for the exposure system and a high production rate, the production rate being in terms of the number of wafers which can be processed during a given time period.
Hybrid alignment procedures are described, for example, in the following published articles: J. Peavey et al, SPIE Proceedings, Vol. 334, p 149 (1982); and F. Ushiyama et al, "Hybrid Alignment: 5:1 Stepper with 1:1 Scanner", SEMICONDUCTOR INTERNATIONAL, Apr., 1985.
The hybrid alignment method requires the provision of two types of alignment markings, each type being required for a respective one of the two systems. For the system involving image reduction, the area required on the substrate for each alignment marking is of the order of 30.mu.. Since this is less than the width of each scribe line, the provision of such alignment markings does not reduce the number of useable chips which can be formed on a given wafer.
On the other hand, the alignment markings for a projection aligner system require more space. One example of the automatic projection alignment markings for this system is illustrated in FIG. 1. These markings include markings 31 which are automatic alignment markings of the projection aligner type which are formed on the semiconductor wafer substrate by either the stepper or the projection aligner system in a preceding step. Markings 31 can be formed to have a convex outer surface in the manner described in F. Ushiyama et al, supra, or can be formed to have a concave configuration.
Markings 32 are present on the glass mask associated with the projection aligner system and can be formed as a positive or negative pattern using chromium. The nature of the pattern then produced on the wafer depends on whether the pattern on the mask is positive or negative or whether use is made of a positive or negative type resist.
Both sets of markings 31 and 32 extend to the right and left parallel to the flat surfaces of the substrate and the mask. The direction of the markings is associated with the crystal orientation of the wafer. The wafer surface is scanned with a laser beam 33 whose axis is substantially perpendicular to the wafer surface. The direction of scanning is indicated by the horizontal arrows. Automatic alignment is achieved when the laser light reflected from the wafer surface indicate that all of the intervals 34, 35, 36 and 37 are equal.
The area required for the alignment markings, 31, 32 has a width, in the vertical direction of FIG. 1, of the order of 160-200.mu., and a length, parallel to the scanning direction, of the order of 600.mu..
In addition, it is common practice in the art to form on a wafer a test element group which includes at least a process monitor transistor which subsequently serves to provide an indication of the quality of the fabrication operation. Generally, the test element group will include components which permit the monitoring of sheet resistance, contact resistance, the resistance associated with field reversal, pattern resolution and deviation, transistor properties, etc. Testing is carried out by contacting appropriate contact points of the test element group by means of pins mounted on a test card to obtain the desired measurements before the wafer is divided into individual chips. The test results permit a determination of whether subsequent tests of electrical properties and chip yield should be performed or not and provide information for subsequent process improvements.
When forming semiconductor layers with the stepper system, it has been found that associating the projection aligner type automatic alignment marks and the test element group pattern with each individual group of semiconductor components formed on the wafer is not desirable because it reduces the number of useable chips which can be formed on a wafer.
Many techniques have been proposed for inserting the automatic alignment markings. For example, Japanese Laid-open Patent No. 60-35514 discloses that automatic alignment markings can be applied by modifying the scribe lines between chips, while Japanese Laid-open Patent No. 60-119724 discloses that the automatic alignment markings can be placed in the spaces between the long sides of adjacent strip chips. However, the latter approach reduces the design freedom associated with the short sides of the strip chips. In fact, the smaller the dimension of the short side, the greater is the reduction in the number of useable chips which can be formed on a given wafer.
FIGS. 2(a)-2(c) illustrate successive steps in the manufacture of integrated circuits according to known procedures.
As shown in FIG. 2(a), a large number of strip chips are to be produced in a plurality of groups 46 on a wafer 45 of generally circular configuration. Each pattern for each group is provided on a glass reticle 48 which provides a pattern for one group which is to be imaged on wafer 45 according to the stepper, or size reduction, system. The pattern, which is imaged in steps on successive regions of wafer 45, includes a plurality of pattern areas 41, each associated with a respective strip chip, and a pattern area 42 containing at least one automatic alignment mark for a subsequent projection aligner step and a mask portion for forming at least the transistor of a process monitor. The resulting process monitor transistor will be used to perform an initial monitoring of the process and pattern area 42 can additionally include other components such as a resistor. The process monitor will serve to provide readings relating to the values of Vth (threshold voltage), contact resistance, diffused resistance, pressure resistance associated with field reversal, and the size of the transistor element. As can be seen, the length of the pattern area 42 is an integral multiple of the length of each strip chip to be produced.
Pattern area 42 is not reproduced on wafer 45 in association with each group of strip chips to be produced. Rather, before imaging of each group 46, pattern 42 on reticle 48 is covered by a shutter 43 in accordance with a predetermined imaging scheme, so that only the strip chip patterns 41 are imaged on wafer 45 in each region 46.
During this phase of one exposure operation, blank regions 44 are left near both the left and right sides of the wafer surface.
In a subsequent step, as shown in FIG. 2(b), shutter 43 is moved in order to additionally expose test element group pattern 42, and then the entire pattern on reticle 48 is imaged in an area portion 47 of each of the areas 44.
In a final stage, depicted in FIG. 2(c), shutter 43 is again displaced in order to cover both pattern 42 and a number of chip patterns 41, leaving exposed a part of the reticle pattern which corresponds to the size of the remaining portions 49 of each of the areas 44, and the portions of the pattern on reticle 48 which remain exposed are then imaged on portions 49 of wafer 45.
This sequence of steps is repeated for each pattern to be successively imaged on wafer 45.
The procedure described above represents a relatively complicated imaging operation requiring a large number of stepper movements to establish the necessary relative position between reticle 48 and wafer 45. Moreover, this procedure requires successive displacements of shutter 43 during the imaging of each pattern on wafer 45. Frequently, the movements of shutter 43 result in the deposition of particles on reticle 48, and these particles will result in the fabrication of defective circuits, thereby significantly reducing the yield of useable chips.